The present invention relates generally to circuitry for controlling power supplies, and more specifically to oscillator circuitry for generating variable duty cycle PWM signals from which power supply operation can be controlled.
As the number and complexity of electronic systems for automotive applications has grown in recent years, so too have power dissipation requirements for such systems. In an attempt to manage and conserve electrical power in the automotive environment, designers of automotive electronic systems have developed switchable power supplies that may themselves be electronically controlled to thereby reduce power dissipation in electrical components connected to such supplies. One particular class of switchable power supplies utilizes a pulse-width modulated (hereinafter xe2x80x9cPWMxe2x80x9d) signal with a variable duty cycle to control the power supply in such a manner as to down regulate battery voltage to certain electrical components under certain operating conditions. An example of one known switchable power supply utilizes a boost supply and a PWM signal with a variable duty cycle to control the switching operation of a power transistor to thereby pulse-width modulate the battery voltage supplied to certain electrical components. In this design, an error amplifier with feedback monitors the boost voltage and compares it to the battery voltage. The output of this error amplifier is compared to an oscillating ramp signal of an oscillation circuit, and the result of this comparison is a PWM signal that is used to control the operation of the power transistor. The comparator thresholds, along with the charge and discharge rates of the ramp signal, control the minimum and maximum duty cycles of the PWM signal.
One example of a known oscillator circuit 10 for generating an oscillating ramp signal, comparing the ramp signal to an error signal provided by an error amplifier, and generating a PWM signal therefrom as just described, is shown in FIG. 1. Referring to FIG. 1, oscillator circuit 10 includes a series-connected resistor ladder comprising resistors R1,R2, R3 and R4, wherein one end of R1 is connected to a supply voltage VCC and one end of R4 is connected to ground potential. The common connection of R1 and R2 defines a first reference voltage VR1 and is connected to an inverting input of a first comparator C1. The common connection of R2 and R3 likewise defines a second reference voltage VR2 and is connected to an inverting input of a second comparator C2, while the common connection of R3 and R4 defines a third reference voltage VR3 and is connected to an inverting input of a third comparator C3. A fourth comparator C4 is also provided and includes an inverting input receiving an error signal ERR from output of an error amplifier (not shown) comparing the boost voltage to the battery voltage. A resistor ROSC is connected at one end to VCC and at an opposite end to one end of a capacitor C having an opposite end connected to ground potential. The common connection of ROSC and C defines an oscillating ramp signal OSC and is connected to the non-inverting inputs of comparators C1-C4 as well as to a collector of a NPN transistor Q4.
The output of comparator C3 defines a comparator voltage VC3 and is fed through an inverter to a xe2x80x9csetxe2x80x9d input S of a first latch circuit L1. A xe2x80x9cresetxe2x80x9d input R of latch circuit L1 receives comparator voltage VC1 defined by an output of comparator C1. Likewise, the output of comparator C2 defines a comparator voltage VC2 and is supplied to a xe2x80x9cresetxe2x80x9d input R of a second latch circuit L2, and the output of comparator C4 defines a comparator voltage VC4 and is supplied to a xe2x80x9csetxe2x80x9d input S of latch circuit L2. A xe2x80x9cQxe2x80x9d output of latch circuit L1 is connected to the base of a NPN transistor Q1 having an emitter connected to ground potential and a collector connected to the base of a NPN transistor Q2, the collector of a NPN transistor Q3 and one end of a current source Ix having an opposite end connected to VCC. The emitter of Q2 is connected to the bases of Q3 and Q4, and the emitters of Q3 and Q4 are connected to the bases of NPN transistors Q8 and Q5 as well as to the collector of Q5. The collector of Q8 is connected to the collector of a NPN transistor Q7 and defines the circuit output PWMOUT, and the base of Q7 is connected to the xe2x80x9cQxe2x80x9d output of latch circuit L2. The emitters of Q5, Q7 and Q8 are connected to ground potential.
Referring now to FIG. 2, which is composed of FIGS. 2A-2G, some of the signals associated with the operation of oscillator circuit 10 of FIG. 1 are illustrated. The outputs VC122 (FIG. 2F) and VC320 (FIG. 2E) of comparators C1 and C3 respectively control the OSC waveform 24 (FIG. 2G) by the use of latch circuit L1 and associated transistor circuitry. The PWM output signal 12 (FIG. 2A) is created by the interaction of the same transistor circuitry (Q1-Q8) and the output voltage VC218 (FIG. 2D) of comparator C2. The variability in the duty cycle of the PWMOUT signal 12 is accomplished by the interaction of the output voltage VC414 (FIG. 2B), which is the comparison of the ERR signal 25 (FIG. 2G) and the OSC signal 24.
The threshold voltages for the OSC signal 24 are VR126 and VR330 (FIG. 2G), and the output voltage VL116 (FI. 2C) of latch circuit L1 provides the maximum duty cycle of the PWMOUT signal 12 when ERR 25 is above the peak of the OSC signal 24. The duty cycle of PWMOUT in this case is dependent upon the ratio of the charge and discharge times of the capacitor C. The minimum duty cycle of PWMOUT 12 occurs when ERR 25 is below the peak of the OSC signal 24, and in this state, the PWMOUT signal 12 is the inverse of VC218 which holds the latch circuit L2 in reset, wherein the threshold voltage for the switching of VC218 is VR228 (FIG. 2G). As ERR 25 increases between the lower and upper peaks of OSC 24, the output of latch circuit L2 is modified by the interaction of VC414 which sets the latch circuit L2.
While the prior art circuit 10 of FIG. 1 is operable as described to provide a variable duty cycle PWM output signal, there are several drawbacks with the structure and operation of this circuit. For example, the minimum and maximum duty cycles of the PWMOUT signal 12 may vary depending upon variations in circuit component operation; i.e., with the charging and discharging times of capacitor C as well as with the operation of comparator C2. In any case, the minimum and maximum duty cycles of the PWMOUT signal 12 are not fixed as would be desirable in a circuit of this type. As another example, many different circuit parameters contribute to the variation of the duty cycle of PWMOUT 12 between the minimum and maximum duty cycles thereof. Accordingly, this variation is subject to multiple sources of error, and very accurate circuit operation therefore cannot be guaranteed or expected. What is therefore needed is an improved oscillator circuit for generating an accurate variable duty cycle PWM signal with fixed minimum and maximum duty cycles. Ideally, such an improved oscillator circuit is provided in accordance with a simplified circuit design utilizing minimum circuitry and minimal signal comparisons.
The foregoing shortcomings of the prior art are addressed by the present invention. In accordance with one aspect of the present invention, an oscillator circuit comprises an oscillation circuit producing a first periodic clock signal as a function of a first capacitor, a second periodic clock signal as a function of a second capacitor and a periodic ramp signal as a function of a third capacitor, a comparator circuit responsive to an error signal and the periodic ramp signal to produce a third clock signal as a function thereof, and a logic circuit responsive to the first, second and third clock signals to produce a periodic output signal as a function thereof.
In accordance with another aspect of the present invention, an oscillator circuit comprises an oscillation circuit producing first and second periodic clock signals and a periodic ramp signal, a comparator circuit responsive to an error signal and the periodic ramp signal to produce a pulse width modulated (PWM) clock signal as a function thereto, and a logic circuit responsive to the PWM clock signal to produce a periodic output signal in accordance with the first clock signal if the PWM clock signal is fixed at a first logic state, in accordance with the second clock signal if the PWM clock signal is fixed at a second opposite logic state, and in accordance with the PWM clock signal if the PWM clock signal is periodically switching between the first and second logic states.
In accordance with a further aspect of the present invention, a method of producing a periodic switching signal comprises the steps of producing a minimum duty cycle periodic clock signal, producing a maximum duty cycle periodic clock signal, producing a periodic ramp signal, producing a pulse width modulated (PWM) clock signal as a function of an error signal and the periodic ramp signal, and producing a periodic output signal in accordance with the minimum duty periodic clock signal if the PWM clock signal is fixed at a first signal level, in accordance with the maximum duty cycle periodic clock signal if the PWM clock signal is fixed at a second opposite signal level, and in accordance with the PWM clock signal if the PWM clock signal is periodically switching between the first and second signal levels.
One object of the present invention is to provide an improved oscillator circuit for generating a periodic pulse-width modulated (PWM) output signal.
Another object of the present invention is to provide such an improved oscillator circuit for generating a PWM output signal as a function of a comparison between a periodic ramp signal and an error signal.
Yet another object of the present invention is to provide such an improved oscillator circuit for generating a PWM output signal as a function of a comparison between a periodic ramp signal and an error signal, wherein the PWM output signal has predefined minimum and maximum duty cycles.
These and other objects of the present invention will become more apparent from the following description of the preferred embodiment.